Incoming frames are stored in RXL2 FIFO which is composed of 2 banks. L2 FIFO enables offloading of PRU (Programmable Real-Time Unit: real-time non-preemptive RISC core) to do other tasks by buffering 16-bit data (8-bit at a time) from L1 FIFO. Hence instead of polling every 160 ns (16-bit) for received data, we can poll every 2.56 us (32*8*10).
Each bank has 32 bytes of data, 16 bytes of status and a 5-bit write pointer. There is one status entry per two bytes. The write pointer gives the info about data entry being written. First 8 registers in the bank hold data and next 4 registers has corresponding status.
A status can be volatile or static. A volatile status is one which is not yet complete, and hence can not be parsed.
The parser task might be required to start parsing in the middle of the FIFO based on where it left parsing in the previous run.
The frames are packed contiguously. The buffer does not switch on each EOF.